The reduction of thermal noise and increase in operation speed that have been accomplished by the miniaturization of CMOS (Complementary MOS) technology have made it possible for a radio communication front-end circuit to be formed of CMOS. The radio communication front-end circuit has been hitherto formed of a compound semiconductor such as gallium arsenide, silicon germanium or the like, or silicon bipolar device.
In recent years, there has been proposed an RF circuit in which a radio front-end circuit including a low noise amplifier has been entirely formed of digital CMOS circuits, and a great advance has been made in digitalization of control and signal processing. This circuit utilizes a feature of the scaled-down CMOS such as ease of integration on a chip with a digital baseband.
Especially due to the development of a ubiquitous network represented by a sensor network, which uses a weak radio frequency band, demands for lower cost and lower power consumption for a wireless IP core have been more and more increased. Importance of an RF circuit technology which promotes formation of a circuit using digital CMOS and digitization of control and signal processing has been increased so as to meet these demands.
As shown in FIG. 1 of Patent Document 1 (JP Patent Kokai Publication No. 2002-374181), for example, in a digital radio receiver, a filter that uses discrete time signal processing is incorporated into a radio frequency region, and the number of expensive off-chip elements such as a surface elastic wave filter before or after a mixer is reduced. The digital radio receiver is manufactured by an existing CMOS integrated circuit fabrication technology. As a result, a radio receiver characterized by low cost and low power consumption is implemented.
As shown in Patent Document 2 (Pamphlet of International Publication No. WO 2006/046632), digitization of control and formation of a circuit using CMOS allow further lower power consumption. A configuration shown in Patent Document 2 will be described below with reference to drawings.
Referring to FIG. 2, it can be seen that the configuration in Patent Document 2 comprises a clock generator 209 that supplies a sampling clock, a carrier wave reproduction circuit 211 for reproducing a carrier wave, a sample and hold circuit 201, a band-pass filter 203, a demodulation circuit 205, and a stop circuit 204. The sample and hold circuit 201 samples an input signal upon reception of the sampling clock supplied through a sampling clock distribution system 212 from the clock generator 209, and then holds the input signal for a predetermined period of time, thereby converting the input signal into a discrete time signal. The band-pass filter 203 suppresses an unwanted aliased component and an undesired frequency component generated by digitization of the signal. The demodulation circuit 205 compares the input signal with the reproduced carrier wave for a very short time to output a baseband signal. The demodulation circuit 205 then sends the baseband signal to physical layer signal processing 210. The stop circuit 204 stops the operations of the demodulation circuit 205, sampling clock distribution system 212, and other amplifiers and filters that consume power of the receiver circuit as necessary upon reception of the demodulated baseband signal.
The sample and hold circuit 201 includes a sampling switch 200 that repeats an on/off operation according to the sampling clock and thereby samples the input signal for each predetermined time, and a sampling capacitor 202 that accumulates and holds the signal output from the sampling switch 200 for a predetermined time.
The stop circuit 204 includes a transmission quality determination means 206, a sampling time determination means 207, and a stop signal supply means 208. The transmission quality determination means 206 receives the baseband signal that has been demodulated and output by the demodulation circuit 205, calculates a demodulation error rate, and then determines whether this demodulation error rate satisfies a value as prescribed by communication standards. The sampling time determination means 207 determines a minimum demodulation time for satisfying the communication standards based on the demodulation error rate calculated by the transmission quality determination means 206. The stop signal supply means 208 supplies a signal that stops the demodulation circuit 205, sampling clock distribution system 212, and other amplifiers and circuit elements of the receiver, based on the demodulation time determined by the sampling time determination means 207.
The signal from the stop signal supply means 208 is supplied to the demodulation circuit 205, sampling clock distribution system 212, and the other amplifiers and filters. A demodulation function and a block such as the sampling clock distribution system that is a power consumption element in the receiver circuit are stopped as necessary.
FIG. 3 is a diagram showing operation waveforms of the circuit (demodulation circuit 205) in FIG. 2. FIG. 4 is a flowchart for explaining an operation of the circuit in FIG. 2. Referring to FIGS. 3 and 4, the operation of the circuit in FIG. 2 will be described in detail. For the sake of simplification, offset quadrature phase shift keying (O-QPSK) in which a baseband signal is band-limited to a sine wave will be herein taken by way of a simple example of digital modulation. In the case of typical quadrature phase shift keying, the phase of the carrier wave is moved in four types of phases of 45 degrees, 135 degrees, 225 degrees, and 315 degrees and digital data is transmitted with these types of phases being respectively associated to binary signals. No particular restriction is, however, imposed on data transition pattern. For this reason, three types of phase transition patterns including ±90 degrees phase shifts and 180 degree phase shift are used. In the case of the offset quadrature phase shift keying, however, the data transition of the 180-degree phase shift is not allowed and thus there remains two types of phase transition patterns comprised of ±90 degrees phase shifts. In addition, when the bandwidth of the baseband signal is limited to the sine wave, a speed at which the phase is moved by modulation is constant, and the envelope of a modulated wave is constant, thereby being simple.
Based on this simplicity of modulation, the phase shift of +90 degrees can be regarded as frequency modulation in which a frequency is super-imposed by a positive value from a carrier wave frequency. The same holds true for the reverse phase shift of −90 degrees.
That is, in the case of a modulation scheme in which a phase shift is made at a certain prescribed speed, it can be also regarded that the frequency modulation is performed from a waveform.
This modulation scheme is adopted in a physical layer of the 802.15.4 standards for Wireless Personal Area Networks, standardized by the Institute of Electrical and Electronics Engineers, inc., for example. A symbol rate is assumed to be Fr. These modulation conditions are assumed to be the same in the following description.
An input signal having a center frequency Fin, which has been frequency-selected and amplified through a radio frequency band selection filter and an amplifier not shown, is supplied to the sample and hold circuit 201.
The sampling switch 200 which is located in an initial stage of the sample and hold circuit 201, and which is driven by the sampling clock of a frequency fs supplied from the clock generator 209 to repeat on/off operation, samples a voltage amplitude value of the input signal for each sampling clock period 1/fs and sends this value to the sampling capacitor 202 in a succeeding stage. The value of the sampled input signal is held in this sampling capacitor 202 for the predetermined time during the sampling clock period 1/fs. The time during which this value of the sampled input signal is held is a value that can be changed according to the duty ratio of the sampling clock, the circuit configuration of the sample and hold circuit 201, and others.
As described above, the input signal is converted to a discrete time signal from a continuous time signal at the sample and hold circuit 201, and is supplied to the band-pass filter 203 and the demodulation circuit 205 located in succeeding stages. Digital signal data processing and circuit operation can be performed after the sample and hold circuit 201.
With the conversion to the discrete time signal, the signal output from this sample and hold circuit 201 includes a large number of frequency components other than the original input center frequency Fin.
As described in the description of the operation of the related art, the reason for this inclusion of the frequency components other than the original input center frequency Fin is that frequency components other than the desired frequency component may be reproduced from the sampled data because data values are made discrete. This phenomenon is generally referred to as “alias”. The band-pass filter 203 in the succeeding stage is employed in order to eliminate aliases and undesired mixed frequency components from other communication standards.
When only a desired frequency component Fc is selected and extracted by the band-pass filter 203 from a large number of aliased components generated at the sample and hold circuit 201, the center frequency of a bandwidth can be converted from Fin to Fc while maintaining the digital baseband signal.
The sample and hold circuit 201 is combined with the band-pass filter 203, thereby performing frequency selection and conversion.
The discrete time signal output from the sample and hold circuit 201 is supplied to the band-pass filter 203 located at the stage succeeding to the sample and hold circuit 201. This band-pass filter 203 is composed by a digital filter that handles a discrete time signal. An infinite impulse response filter that returns (feedbacks) a signal output from the filter to an input of the filter and uses the fed-back signal for calculation, and a finite impulse response filter that does not feedback an output signal can be both used as the band-pass filter 203. The filter used herein selects and extracts only a signal band used in communication, outputs the extracted signal band, and supplies the extracted signal band to the demodulation circuit 205 in a succeeding stage. Therefore, the filter must be able to exclude signals from other communication standards and signals of neighboring channels of the same standard.
In view of this respect, it is required that the band-pass filter 203 can pass a signal of a narrow bandwidth and further have a high frequency cutoff characteristic. The reason for that requirement is that when a signal of a channel other than a desired channel is received during demodulation, the signal of the channel other than the desired channel cannot be separated due to the characteristics of the demodulation circuit 205, as will be described later, and interferes with a demodulating operation.
Generally, the infinite impulse response filter (IIR: Infinite Impulse Response Filter) satisfies the specifications using a low filter order ranging from fourth to sixth order. When the signal of the narrow bandwidth is selectively passed, filter poles come close. The filter may thereby become an unstable filter accompanied by a risk of oscillation.
On the other hand, the finite impulse response filter (FIR: Finite Impulse Response Filter) may have a filter length of approximately ten times that of the infinite impulse response filter having same characteristics, though there is no possibility of oscillation. Thus, a chip unit price may be increased.
The waveform of the modulated signal that has undergone frequency-conversion and selection is compared with the waveform of a reproduced carrier wave 213 that serves as a reference, in the demodulation circuit 205. The baseband signal is thereby extracted and demodulated.
Reproduction of the carrier wave will be herein described. Generally, in digital radio communication, data transmission is performed in packet format. It is stipulated that, before transmission of actual data, a fixed training signal which is referred to as a preamble is flown at the beginning portion of the packet for a fixed time.
In accordance with this preamble, the receiver circuit can prepare an environment necessary for actual data reception, such as frequency locking and phase synchronization by a frequency synthesizer. The receiver circuit can thereby perform demodulation.
This makes it possible to reproduce the carrier wave for a frequency used in the communication and then supply the carrier wave to the demodulation circuit 205 for demodulation, by utilizing the preamble. The sequence of operations mentioned above is performed by the carrier wave reproduction circuit 211.
The modulated signal, the frequency of which has been converted from Fin to Fc by the sample and hold circuit 201 and the band-pass filter 203 is supplied to the demodulation circuit 205, together with the carrier wave 213 reproduced by the carrier wave reproduction circuit 211. The baseband signal is thereby extracted and then demodulated.
FIG. 3 is a diagram showing operation waveforms of the demodulation circuit 205. As shown in FIG. 3, during 1/Fr where modulation is performed for one symbol, the demodulation circuit 205 is activated for just 1/Fc which corresponds to one period of the center frequency of the modulated signal, and the waveform corresponding to one wave portion of the modulated signal is read.
At a same time t, the waveform of the reproduced carrier wave 213 is also read. In this example, a case is considered where the phase of the reproduced carrier wave at the time t is zero and the phase of the received modulated signal is shifted to +90 degrees. As described in the description of the modulation scheme, it can be considered that when the phase shift of +90 degrees is made, frequency modulation of a particular positive value Δf alone is applied.
Based on this conception, if it is assumed that a sine wave which oscillates from a ground point 0 to a power supply voltage Vdd is supplied, and a reproduced carrier wave A(t) at the certain time t is expressed as:A(t)=(Vdd/2){1+sin(2π(Fct)}
Then, a modulated wave A′(t), which has undergone a phase shift of +90 degrees is given by:A′(t)=(Vdd/2)[1+sin {2π(Fc+Δf)t}]
When the phase of the reproduced carrier wave A(t) at the time t is 0, the modulated wave A′(t) is expressed as follows, based on simple calculation of a sine wave:A′(t)=(Vdd/2)[1+sin {2π(1+Δf/Fc)N}]
where N is an integer.
When the waveform reading time t is close to a symbol start time 0 and an input frequency Fc is sufficiently faster than a change speed Δf of the baseband signal waveform, the following relation holds:(Vdd/2)<A′(t)<Vdd 
With a comparison circuit which determines whether the voltage amplitude of the modulated wave at time t is greater than or smaller than Vdd/2, it is possible to determine whether modulation of the phase shift of +90 degrees or modulation of the phase shift of −90 degrees is being performed. Demodulation can be thereby performed.
The phase at time t does not need to be 0. When the number of division from the ground point to the power supply voltage is increased as necessary to read the waveform using all of sample points between 0 and 1/Fc, waveform comparison can be made at any carrier wave phase, and demodulation can be thereby performed. The time t must be selected with sufficient delay from the symbol start point so that the inter-symbol interference by a multipath propagation delay may be avoided. As soon as the demodulation is completed, the demodulation circuit 205 is quickly stopped again.
The demodulated baseband signal is sent to the physical layer signal processing 210, and, at the same time is also sent to the transmission quality determination means 206.
The transmission quality determination means 206 finds the demodulation error rate and determines whether or not the demodulation error rate satisfies the prescribed value of the communication standard.
Generally, in the case of packet communication, before the transmission of actual data is performed, the preamble is transmitted and then a fixed training signal for determining a transmission state is sent within the packet. The fixed training signal can be utilized when finding the demodulation error.
When the demodulation error rate found by the transmission quality determination means 206 does not satisfy the prescribed value of the communication standard, the demodulation time is increased from 1/Fc to 2/Fc in the sampling time determination means 207. This 2/Fc is taken as the demodulation time for the next symbol.
According to the demodulation time for the next symbol that has thus been determined, the signal that stops the operations of the demodulation circuit 205, sampling clock distribution system 212, and the other amplifier and filter is supplied from the stop signal supply means 208. Then, the operations of the demodulation circuit 205 and other block functions are stopped for the next symbol.
The demodulation time is successively extended to 3/Fc, 4/Fc, and so on one by one, when the demodulation error rate does not satisfy the communication standard despite extension of the demodulation time to 2/Fc for the next symbol.
This operation allows the circuit stopping time to be adaptively changed according to the transmission quality. A flow of this operation will be shown in FIG. 4.
Next, the effect described in Patent Document 2 will be described. In this technology, the sampling clock is supplied to the sample and hold circuit 201 and power is supplied to the demodulation circuit 205 and the others for only a minimum time necessary for demodulation. Then, the operation of the receiver circuit is stopped for the remaining time. Thus, power consumption of the receiver circuit can be substantially reduced.
Consider a case where a modulated signal is supplied to the demodulation circuit at Fc=100 MHz in a standard in which the modulation time 1/Fr is prescribed to be 500 nanoseconds. In this case, if it is assumed that the time that is spent in detection of a phase modulated is 1/Fc=10 nanoseconds and each of a rise and fall of the circuit can be performed in one nanosecond. Then, power consumption of the demodulation circuit is [(10+1+1)/500]*100=2.4%, which is substantially lower than in a case where the circuit is operated continuously.
In the technology of Patent Document 1, for example, the circuit needs to be operated over an entire data symbol reception period.
On the other hand, in the technology in Patent Document 2, reduced power consumption can be achieved by adaptively stopping the circuit within a symbol period according to the transmission state or communication quality.
Patent Document 1:
    JP Patent Kokai Publication No. JP-P2002-374181APatent Document 2:    International Publication No. WO2006/046632A1